XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 143

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Block RAM Applications
Block RAM Timing Model
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Instantiation of Additional Block RAM Primitives
Creating Larger RAM Structures
R
Table 4-7
Table 4-7: Single-Port Block RAM Primitives
The RAM_Ax templates (with x = 1, 2, 4, 9, 18, or 36) are single-port modules and
instantiate the corresponding RAMB16_Sx module.
RAM_Ax_By templates (with x = 1, 2, 4, 9, 18, or 36 and y = = 1, 2, 4, 9, 18, or 36) are dual-
port modules and instantiate the corresponding RAMB16_Sx_Sy module.
Block RAM columns have special routing to create wider/deeper blocks with minimal
routing delays. Wider or deeper RAM structures are achieved with a smaller timing
penalty than is encountered when using normal routing resources.
The CORE Generator software offers the designer an easy way to generate wider and
deeper memory structures using multiple block RAM instances. This program outputs
VHDL or Verilog instantiation templates and simulation models, along with an EDIF file
for inclusion in a design.
This section describes the timing parameters associated with the block RAM in Virtex-4
devices (illustrated in
Data Sheet
for reference.
RAMB16_S1
RAMB16_S2
RAMB16_S4
RAMB16_S9
RAMB16_S18
RAMB16_S36
lists all of the available single-port primitives for synthesis and simulation.
and the Timing Analyzer (TRCE) report from Xilinx software are also available
Primitive
Figure
www.xilinx.com
4-12). The switching characteristics section in the
Port Width
(16+2)
(32+4)
(8+1)
1
2
4
Block RAM Applications
Virtex-4
143