XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 192

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
192
Shift Registers (Available in SLICEM only)
A SLICEM function generator can also be configured as a 16-bit shift register without using
the flip-flops available in a slice. Used in this way, each LUT can delay serial data
anywhere from one to 16 clock cycles. The SHIFTIN and SHIFTOUT lines cascade LUTs to
form larger shift registers. The four left-hand LUTs (in SLICEM) of a single CLB are thus
cascaded to produce delays up to 64 clock cycles. It is also possible to combine shift
registers across more than one CLB. The resulting programmable delays can be used to
balance the timing of data pipelines.
Applications requiring delay or latency compensation use these shift registers to develop
efficient designs. Shift registers are also useful in synchronous FIFO and content-
addressable memory (CAM) designs. To quickly generate a Virtex-4 FPGA shift register
without using flip-flops (i.e., using the SRL16 element(s)), use the CORE Generator™ tool
RAM-based shift-register module.
The write operation is synchronous with a clock input (CLK) and an optional clock enable,
as shown in
A[3:0]. The configurable 16-bit shift register cannot be set or reset. The read is
asynchronous; however, a storage element or flip-flop is available to implement a
synchronous read. By placing this flip-flop, the shift register performance is improved by
decreasing the delay into the clock-to-out value of the flip-flop. However, an additional
clock latency is added. Any of the 16 bits can be read out asynchronously by varying the
LUT address. This is useful in making smaller shift registers (less than 16 bits.) For
example, when building an 8-bit shift register, simply set the addresses to the 8th bit.
Figure
SHIFTIN (D)
CE (SR)
D(BY)
A[3:0]
5-9. A dynamic read access is performed through the 4-bit address bus,
CLK
Figure 5-9: Shift Register Configurations
www.xilinx.com
4
WE
CK
A[4:1]
WS
SRLC16
WSG
SHIFT-REG
MC15
DI
D
SHIFTOUT (Q15)
(optional)
D
Q
UG070 (v2.6) December 1, 2008
UG070_5_09_071504
Output (Q)
Registered
Output
Virtex-4 FPGA User Guide
R