XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 47

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
BUFG VHDL and Verilog Templates
R
Declaring Constraints in UCF File
VHDL Template
The following examples illustrate the instantiation of the BUFG module in VHDL and
Verilog.
endmodule;
//Example BUFGCTRL instantiation
BUFGCTRL U_BUFGCTRL (
// Declaring constraints in Verilog
// synthesis attribute INIT_OUT of U_BUFGCTRL is 0;
// synthesis attribute PRESELECT_I0 of U_BUFGCTRL is FALSE;
// synthesis attribute PRESELECT_I1 of U_BUFGCTRL is FALSE;
// synthesis attribute LOC of U_BUFGCTRL is "BUFGCTRL_X#Y#";
// where # is valid integer locations of BUFGCTRL
INST "U_BUFGCTRL" INIT_OUT = 0;
INST "U_BUFGCTRL" PRESELECT_I0 = FALSE;
INST "U_BUFGCTRL" PRESELECT_I1 = FALSE;
INST "U_BUFGCTRL" LOC = BUFGCTRL_X#Y#;
where # is valid integer locations of BUFGCTRL
--Example BUFG declaration
component BUFG
port(
);
end component;
--Example BUFG instantiation
U_BUFG : BUFG
Port map (
--Declaring constraints in VHDL file
attribute LOC : string;
attribute LOC of U_BUFG: label is "BUFGCTRL_X#Y#";
--where # is valid integer locations of BUFGCTRL
.O(user_o),
.CE0(user_ce0),
.CE1(user_ce1),
.I0(user_i0),
.I1(user_i1),
.IGNORE0(user_ignore0),
.IGNORE1(user_ignore1),
.S0(user_s0),
.S1(user_s1)
);
O: out std_ulogic;
I: in
O => user_o,
I0 => user_i
);
std_ulogic
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VHDL and Verilog Templates
47