XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 357

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Output DDR Primitive (ODDR)
R
Figure 7-25
signals.
ODDR primitive.
Table 7-11: ODDR Port Signals
Table 7-12: ODDR Attributes
Q
C
CE
D1 and D2
R
S
DDR_CLK_EDGE
INIT
SRTYPE
Attribute Name
Name
Port
Table 7-12
shows the ODDR primitive block diagram.
Data output (DDR)
Clock input port
Clock enable port
Data inputs
Reset
Set
describes the various attributes available and default values for the
Function
Figure 7-25: ODDR Primitive Block Diagram
respect to clock edge
Sets the initial value for Q port
Set/Reset type with respect to clock (C)
Sets the ODDR mode of operation with
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CE
D1
D2
C
ODDR register output.
ODDR register inputs.
The C pin represents the clock input pin.
CE represents the clock enable pin. When asserted Low,
this port disables the output clock driving port Q.
Synchronous/Asynchronous reset pin. Reset is asserted
High.
Synchronous/Asynchronous set pin. Set is asserted
High.
Description
R
S
ODDR
ug070_7_25_080104
Table 7-11
Description
Q
OPPOSITE_EDGE
(default), SAME_EDGE
0 (default), 1
ASYNC, SYNC (default)
lists the ODDR port
Possible Values
OLOGIC Resources
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