XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 373

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XC4VFX12-10SFG363C

Manufacturer Part Number
XC4VFX12-10SFG363C
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r

Specifications of XC4VFX12-10SFG363C

Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
363-FBGA, FCBGA
Package
363FCBGA
Family Name
Virtex®-4
Device Logic Units
12312
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
240
Ram Bits
663552
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC4VFX12-10SFG363C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VFX12-10SFG363C
Manufacturer:
XILINX
0
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
INTERFACE_TYPE Attribute
Table 8-3: Allowable Data Widths
When the DATA_WIDTH is set to widths larger than six, a pair of ISERDES must be
configured into a master-slave configuration. See
expansion is not allowed in memory mode.
The INTERFACE_TYPE attribute determines whether the ISERDES is configured in
memory or networking mode. The allowed values for this attribute are MEMORY or
NETWORKING. The default mode is MEMORY. It is recommended to use the Memory
Interface Generator (MIG) when using ISERDES in Memory mode.
When INTERFACE_TYPE is set to NETWORKING, the Bitslip submodule is available and
the OCLK port is unused. Even if the Bitslip module is not used in networking mode,
BITSLIP_ENABLE must be set to TRUE, and the Bitslip port can be tied Low to disable
Bitslip operation. When set to MEMORY, the Bitslip submodule is not available
(BITSLIP_ENABLE must be set to FALSE), and the OCLK port can be used.
Figure 8-6
INTERFACE_TYPE
NETWORKING
Figure 8-6: Internal Connections of ISERDES When in Memory Mode
CLKDIV
OCLK
MEMORY
illustrates the ISERDES internal connections when in Memory mode.
CLK
D
ICE
ICE
FF0
FF1
www.xilinx.com
Input Serial-to-Parallel Logic Resources (ISERDES)
DATA_RATE
DDR
DDR
ICE
ICE
SDR
SDR
FF2
FF3
FF4
FF5
“ISERDES Width Expansion.”
Allowable Data Widths
2, 3, 4, 5, 6, 7, 8
FF6
FF7
FF8
FF9
4, 6, 8, 10
ug070_8_17_041007
None
4
Q1
Q2
Q3
Q4
Width
373

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