XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 66

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Digital Clock Managers (DCMs)
Table 2-6: DCM Attributes (Continued)
66
DCM_AUTOCALIBRATION
DCM_PERFORMANCE_MODE
DESKEW_ADJUST
DFS_FREQUENCY_MODE
DLL_FREQUENCY_MODE
DUTY_CYCLE_CORRECTION
FACTORY_JF
PHASE_SHIFT
STARTUP_WAIT
DCM Attribute Name
CLK_FEEDBACK Attribute
The CLK_FEEDBACK attribute determines the type of feedback applied to the CLKFB.
The possible values are 1X or NONE. The default value is 1X. When this attribute is set to
1X, the CLKFB pin must be driven by CLK0. When this attribute is set to NONE, the
CLKFB pin must be unconnected.
When this attribute is TRUE, the
DCM is protected from the effects
of negative bias temperature
instability (NBTI). This attribute
cannot be set to FALSE unless
CLKIN and CLKFB (if external
feedback is used) are guaranteed
to never stop. The macro can also
be disabled if the user can
guarantee to hold DCM in reset
during clock stoppage. If this
attribute is set to FALSE, the reset
requirement is three clock cycles.
Allows selection between
maximum frequency/ minimum
jitter and low frequency/maximum
phase-shift range.
Affects the amount of delay in the
feedback path, and should be used
for source-synchronous interfaces.
Specifies the frequency mode of the
frequency synthesizer.
Specifies the frequency mode of the
DLL.
Controls the DCM 1X outputs
(CLK0, CLK90, CLK180, and
CLK270), to exhibit a 50/50 duty
cycle. Leave this attribute set at the
default value.
Controls the DCM tap update rate.
Value depends on
DLL_FREQUENCY_MODE setting.
Specifies the phase-shift numerator.
The value range depends on
CLKOUT_PHASE_SHIFT and
clock frequency.
When this attribute is set to TRUE,
the configuration startup sequence
waits in the specified cycle until the
DCM locks.
Description
www.xilinx.com
Boolean: TRUE or FALSE
String: “MAX_SPEED” or
“MAX_RANGE”
String:
“SYSTEM_SYNCHRONOUS”
or
“SOURCE_SYNCHRONOUS”
String: “LOW” or “HIGH”
String: “LOW” or “HIGH”
Boolean: TRUE or FALSE
BIT_VECTOR
Integer:
–255 to 255
or
0 to 1023
Boolean: FALSE or TRUE
Values
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
TRUE
MAX_SPEED
SYSTEM_
SYNCHRONOUS
LOW
LOW
TRUE
F0F0
0
FALSE
Default Value
R