XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 130

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
Block RAM Initialization in VHDL or Verilog Code
Block RAM VHDL and Verilog Templates
130
RAMB16 VHDL Template
The LOC properties use the following form:
The RAMB16_X0Y0 is the bottom-left block RAM location on the device. If RAMB16 is
constrained to RAMB16_X#Y#, the FIFO cannot be constrained to FIFO16_X#Y# since they
share a location. An example location constraint is shown in the
Verilog Templates”
Block RAM memory attributes and content can be initialized in VHDL or Verilog code for
both synthesis and simulation by using generic maps (VHDL) or defparams (Verilog)
within the instantiated component. Modifying the values of the generic map or defparam
affects both the simulation behavior and the implemented synthesis results.
The following template is a RAMB16 example in both VHDL and Verilog. This primitive is
the building block for all different sizes of block RAM.
LOC = RAMB16_X#Y#
--
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--
Library UNISIM;
use UNISIM.vcomponents.all;
--
-- RAMB16: Virtex-4 16k+2k Parity Paramatizable Block RAM
-- Virtex-4 FPGA User Guide
RAMB16_inst : RAMB16
generic map (
<--Cut code below this line and paste into the architecture body-->
declaration
declaration
Copy the following two statements and paste them before the
Entity declaration, unless they already exist.
primitives : primitives and points to the models that will be used
instance
Library
DOA_REG => 0, -- Optional output registers on the A port (0 or 1)
DOB_REG => 0, -- Optional output registers on the B port (0 or 1)
RAMB16
Xilinx
INIT_A => X"000000000", --
INIT_B => X"000000000", --
INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output
registers (TRUE or FALSE)
VHDL
code
for
section.
: to be added before the entity declaration. This library
: In addition to adding the instance declaration, a use
: following instance declaration needs to be placed in
: after the "=>" assignment can be changed to properly
: To incorporate this function into the design,
: the architecture body of the design code. The
: (RAMB16_inst) and/or the port declarations
: reference and connect this function to the design.
: All inputs and outputs must be connected.
: statement for the UNISIM.v components library needs
: contains the component declarations for all Xilinx
: for simulation.
www.xilinx.com
Initial values on A output port
Initial values on B output port
UG070 (v2.6) December 1, 2008
“Block RAM VHDL and
Virtex-4 FPGA User Guide
R