XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 404

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

GTL
H
HSTL
HyperTransport
I
I/O standards
I/O tile
IBUF
IBUFDS
IBUFG
IBUFGDS
IDDR
IDELAY
404
defined
GTL_DCI
GTLP
GTLP_DCI
defined
class I
class I (1.8V)
class II
class II (1.8V)
class III
class III (1.8V)
class IV
class IV (1.8V)
CSE differential HSTL class II
DIFF_HSTL
LDT
bank rules
compatibility
differential I/O
single-ended I/O
ILOGIC
IOB
OLOGIC
PULLUP/PULLDOWN/KEEPER
OPPOSITE_EDGE mode
ports
primitive
SAME_EDGE mode
SAME_EDGE_PIPELINED mode
defined
attributes
delay mode
261
247
263
323
274
251
326
26
233
248
331
233
296
,
26
,
327
262
265
247
261
263
331
266
276
,
270
271
233
233
248
327
234
334
261
,
302
262
365
281
273
274
299
278
279
234
234
325
323
268
,
IDELAYCTRL
ILOGIC
IOB
IOBDELAY
IOBUF
IOBUFDS
ISERDES
L
LDT
LVCMOS
LVDCI
IDELAYCTRL
increment/decrement
ports
primitive
reset
switching characteristics
timing
instantiating
location
primitive
REFCLK
IDDR
SR
switching characteristics
timing
233
defined
PULLUP/PULLDOWN/KEEPER
defined
attributes
bitslip
IDELAY
ports
primitive
serial-to-parallel converter
switching characteristics
timing models
width expansion
See HyperTransport
defined
defined
LVDCI_DV2
source termination
251
248
257
321
233
fixed
variable
zero-hold time
RDY port
BITSLIP_ENABLE attribute
IDELAYCTRL
365
333
255
249
333
367
323
366
334
329
234
365
255
257
,
374
www.xilinx.com
343
321
341
,
332
341
367
372
341
332
,
368
368
,
343
332
258
351
,
344
341
379
,
388
,
383
375
345
304
341
332
296
333
334
331
379
365
,
376
372
LVDS
LVPECL
LVTTL
M
modes
N
NO_CHANGE mode
O
OBUF
OBUFDS
OBUFT
OBUFTDS
ODDR
OLOGIC
OSERDES
P
parallel-to-serial converter
PCI
PFDM
PMCD
260
defined
LVDS_25_DCI
LVDSEXT_25_DCI
defined
defined
source-synchronous
system-synchronous
PULLUP/PULLDOWN/KEEPER
clock forwarding
OPPOSITE_EDGE mode
ports
primitive
SAME_EDGE mode
timing
parallel-to-serial converter
switching characteristics
timing
DDR
SDR
PCI33
PCI66
PCIX
294
UG070 (v2.6) December 1, 2008
247
251
315
354
253
247
297
233
248
386
387
357
260
386
249
260
260
Virtex-4 FPGA User Guide
294
297
253
359
394
,
357
351
,
395
295
119
356
295
74
356
73
386
394
354
386
R