XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 187

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Look-Up Table (LUT)
Storage Elements
Virtex-4 FPGA function generators are implemented as 4-input look-up tables (LUTs).
There are four independent inputs for each of the two function generators in a slice (F and
G). The function generators are capable of implementing any arbitrarily defined four-input
Boolean function. The propagation delay through a LUT is independent of the function
implemented. Signals from the function generators can exit the slice (through the X or Y
output), enter the XOR dedicated gate (see
carry-logic multiplexer (see
element, or go to the MUXF5.
In addition to the basic LUTs, the Virtex-4 FPGA slices contain multiplexers (MUXF5 and
MUXFX). These multiplexers are used to combine up to eight function generators to
provide any function of five, six, seven, or eight inputs in a CLB. The MUXFX is either
MUXF6, MUXF7, or MUXF8 according to the position of the slice in the CLB. The MUXFX
can also be used to map any function of six, seven, or eight inputs and selected wide logic
functions. Functions with up to nine inputs (MUXF5 multiplexer) can be implemented in
one slice (see
LUTs within the same CLB or across different CLBs making logic functions with even more
input variables.
The storage elements in a Virtex-4 FPGA slice can be configured as either edge-triggered
D-type flip-flops or level-sensitive latches. The D input can be driven directly by a LUT
output via the DX or DY multiplexer, or by the slice inputs bypassing the function
generators via the BX or BY input.
The control signals clock (CLK), clock enable (CE) and set/reset (SR) are common to both
storage elements in one slice. All of the control signals have independent polarity. Any
inverter placed on a control input is automatically absorbed. The clock-enable signal (CE)
is active High by default. If left unconnected, the clock enable defaults to the active state.
In addition to clock (CLK) and clock enable (CE) signals, each slice has set and reset signals
(SR and BY slice inputs). SR forces the storage element into the state specified by the
attribute SRHIGH or SRLOW. SRHIGH forces a logic High when SR is asserted. SRLOW
forces a logic Low. When SR is used, an optional second input (BY) forces the storage
element into the opposite state via the REV pin. The reset condition is predominant over
the set condition. (See
Resources” in Chapter
The initial state after configuration or global initial state is defined by a separate INIT0 and
INIT1 attribute. By default, setting the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1.
For each slice, set and reset can be synchronous or asynchronous. Virtex-4 devices can set
INIT0 and INIT1 independent of SRHIGH and SRLOW.
Figure 5-14, page
Figure
7.
www.xilinx.com
“Fast Lookahead Carry
5-4.) The truth tables for SR are described
198). Wide function multiplexers can effectively combine
“Arithmetic
Logic”), feed the D input of the storage
Logic”), enter the select line of the
in“ILOGIC
CLB Overview
187