XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 80

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Digital Clock Managers (DCMs)
80
Phase-Shift Overflow
Phase-Shift Characteristics
The phase-shift overflow (DO[0]) status signal is asserted when either of the following
conditions are true.
The DCM is phase-shifted beyond the allowed phase-shift value. In this case, the phase-
shift overflow signal will be asserted High when the phase shift is decremented beyond –
255 and incremented beyond +255 for VARIABLE_CENTER mode, incremented beyond
+255 for VARIABLE_POSITIVE mode, or decremented beyond 0 and incremented beyond
1023 for DIRECT mode.
The DCM is phase-shifted beyond the absolute range of the phase-shift delay line. In this
case, the phase-shift overflow signal will be assert High when the phase-shift in time (ns)
exceeds the ±FINE_SHIFT_RANGE/2 in the VARIABLE_CENTER mode, the
+FINE_SHIFT_RANGE in the VARIABLE_POSITIVE mode, or exceeds 0 to
+FINE_SHIFT_RANGE in the DIRECT mode. The phase-shift overflow signal can toggle
once it is asserted. The condition determining if the delay line is exceeded is calibrated
dynamically. Therefore, at the boundary of exceeding the delay line, it is possible for the
phase-shift overflow signal to assert and de-assert without a change in phase shift. Once
asserted, it will remain asserted for at least 40 CLKIN cycles. If the DCM is operating near
the FINE_SHIFT_RANGE limit, do not use the phase-shift overflow signal as a flag to
reverse the phase shift direction. When the phase-shift overflow is asserted, de-asserted,
then asserted again in a short phase shift range, it can falsely reverse the phase shift
direction. Instead, use a simple counter to track the phase shift value and reverse the phase
shift direction (PSINCDEC) only when the counter reaches a previously determined
maximum/minimum phase shift value. For example, if the phase shift must be within 0 to
128, set the counter to toggle PSINCDEC when it reaches 0 or 128.
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•
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PSINCDEC
Offers fine-phase adjustment with a resolution of ±1/256 of the clock period (or ± one
DCM_TAP, whichever is greater). It can be dynamically changed under user control.
The phase-shift settings affect all nine DCM outputs.
V
In either fixed or variable mode, the phase-shift range can be extended by choosing
CLK90, CLK180, or CLK270, rather than CLK0, choosing CLK2X180 rather than
CLK2X, or choosing CLKFX180 rather than CLKFX. Even at 25 MHz (40 ns period),
the fixed mode coupled with the various CLK phases allows shifting throughout the
entire input clock period range.
MAX_RANGE mode extends the phase-shift range.
PSDONE
CC
PSCLK
PSEN
and temperature do not affect the phase shift except in direct phase-shift mode.
Figure 2-7: Phase-Shift Timing Diagram
www.xilinx.com
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
UG070_2_06_031208
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