XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 219

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Creating Larger RAM Structures
VHDL and Verilog Templates
Wider and/or deeper memory structures can be created using multiple distributed RAM
instances.
provided to implement n-bit-wide memories.
Table 5-12: VHDL and Verilog Submodules
By using the read/write port for the write address and the second read port for the read
address, a FIFO that can read and write simultaneously is easily generated. Simultaneous
access doubles the effective throughput of the memory.
VHDL and Verilog templates are available for all single-port and dual-port primitives. The
number in each template indicates the number of bits (for example, RAM_16S is the
template for the 16 x 1-bit RAM); S indicates single-port, and D indicates dual-port.
In VHDL, each template has a component declaration section and an architecture section.
Each part of the template should be inserted within the VHDL design file. The port map of
the architecture section should include the design signal names.
The single-port templates are:
•
•
•
The dual-port templates are:
•
Templates for the RAM_16S module are provided in VHDL and Verilog code as examples.
VHDL Template
XC4V_RAM16XN_D
RAM_16S
RAM_32S
RAM_64S
RAM_16D
--
-- Module: RAM_16S
--
-- Description: VHDL instantiation template
--
--
--
--
-- Device: Virtex-4 Family
--
---------------------------------------------------------------------
--
-- Components Declarations:
--
XC4V_RAM16XN_S
XC4V_RAM32XN_S
XC4V_RAM64XN_S
Submodules
Table 5-12
shows the generic VHDL and Verilog distributed RAM examples
Distributed RAM
Single Port 16 x 1
can be used also for RAM16X1S_1
www.xilinx.com
RAM16X1D
RAM16X1S
RAM32X1S
RAM64X1S
Primitive
CLB Primitives and Verilog/VHDL Examples
16 words x n-bit
32 words x n-bit
64 words x n-bit
16 words x n-bit
Size
single-port
single-port
single-port
dual-port
Type
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