XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 160

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
160
Case 3: Reading From a Full FIFO
Clock Event 2: Write Operation, and Assertion of FULL Signal
The FULL signal pin is asserted when the FIFO is full.
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•
•
If the FIFO is full and a read followed by a write is performed, the FULL signal remains
asserted.
Clock Event 3: Write Operation and Assertion of Write Error Signal
The write error signal pin is asserted when data going into the FIFO is not written because
the FIFO is in a FULL state.
•
•
•
Clock Event 4: Write Operation and Deassertion of Write Error Signal
WRERR) is deasserted when a user stops trying to write into a full FIFO.
•
•
The write error signal is asserted/deasserted at every write-clock positive edge. As long as
both the write enable and FULL signals are true, write error will remain asserted.
Prior to the operations performed in
WRCLK
RDCLK
AFULL
WREN
RDEN
FULL
At time T
inputs of the FIFO.
Write enable remains asserted at the WREN input of the FIFO.
At time T
the FULL output pin of the FIFO.
At time T
inputs of the FIFO.
Write enable remains asserted at the WREN input of the FIFO.
At time T
WRERR output pin of the FIFO. Data 05 is not written into the FIFO.
At time T
WREN input of the FIFO.
At time T
WRERR output pin of the FIFO.
DO
FDCK_DI
FCKO_FULL
FDCK_DI
FCKO_WRERR
FCCK_WREN
FCKO_WRERR
1
T
FCCK_RDEN
, before clock event 2 (WRCLK), data 04 becomes valid at the DI
, before clock event 3 (WRCLK), data 05 becomes valid at the DI
00
T
Figure 4-19: Reading From a Full FIFO
, one clock cycle after clock event 2 (WRCLK), FULL is asserted at
FCKO_DO
, before clock event 4 (WRCLK), write enable is deasserted at the
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, after clock event 3 (WRCLK), a write error is asserted at the
, after clock event 4 (WRCLK), write error is deasserted at the
01
Figure
2
02
3
4-19, the FIFO is completely full.
T
FCKO_FULL
03
T
FCKO_DO
UG070 (v2.6) December 1, 2008
04
Virtex-4 FPGA User Guide
4
05
ug070_4_19_071204
T
FCKO_AFULL
06
R