XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 26

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Clock Resources
26
Global Clock Inputs
Global Clock Input Buffer Primitives
Understanding the signal path for a global clock expands the understanding of the various
global clock resources. The global clocking resources and network consist of the following
paths and components:
•
•
•
•
Virtex-4 FPGAs contain specialized global clock input locations for use as regular user
I/Os if not used as clock inputs. The number of clock inputs varies with the device size.
Smaller devices contain 16 clock inputs, while larger devices have 32 clock inputs.
Table 1-1
Table 1-1: Number of Clock I/O Inputs by Device
Clock inputs can be configured for any I/O standard, including differential I/O standards.
Each clock input can be either single-ended or differential. All 16 or 32 clock inputs can be
differential if desired. When used as outputs, global clock input pins can be configured for
any output standard except LVDS and HT output differential standards. Each global clock
input pin supports any single-ended output standard or any CSE output differential
standard.
The primitives in
Table 1-2: Clock Buffer Primitives
These two primitives work in conjunction with the Virtex-4 FPGA I/O resource by setting
the IOSTANDARD attribute to the desired standard. Refer to
Compatibility” Table 6-38
Notes:
1. The XC4VLX40 and XC4VLX60 in the FF668 package only have 16 clock input pins.
2. The XC4VFX100 in the FF1152 package only has 16 clock input pins.
XC4VLX15, XC4VLX25
XC4VSX25, XC4VSX35
XC4VFX12, XC4VFX20, XC4VFX40, XC4VFX60
XC4VLX40
XC4VLX160, XC4VLX200
XC4VSX55
XC4VFX100
IBUFG
IBUFGDS
Global Clock Inputs
Global Clock Buffers
Clock Tree and Nets - GCLK
Clock Regions
Primitive
summarizes the number of clock inputs available for different Virtex-4 devices.
(1)
(2)
, XC4VLX60
, XC4VFX140
Table 1-2
Device
(1)
www.xilinx.com
for a complete list of possible I/O standards.
, XC4VLX80, XC4VLX100,
are different configurations of the input clock I/O input buffer.
Input
I, IB
I
Output
O
O
Input clock buffer for single-ended I/O
Input clock buffer for differential I/O
16
32
Number of Clock I/O Inputs
UG070 (v2.6) December 1, 2008
Description
Chapter 6, “I/O
Virtex-4 FPGA User Guide
R