XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 347

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Verilog Use Model
-- The user either declares the LOC constraints in the
-- VHDL design file, or in the UCF file.
-- Declaring LOC constraints in the VHDL file.
attribute loc : string;
attribute loc of dlyctrl_1:label is "IDELAYCTRL_X0Y0";
attribute loc of dlyctrl_2:label is "IDELAYCTRL_X0Y1";
.
.
.
attribute loc of dlyctrl_n:label is "IDELAYCTRL_XnYn";
-- Declaring LOC constraints in the UCF file.
INST "dlyctrl_1" LOC=IDELAYCTRL_X0Y0;
INST "dlyctrl_2" LOC=IDELAYCTRL_X0Y1;
.
.
.
INST "dlyctrl_n" LOC=IDELAYCTRL_XnYn;
// Multiple instances of IDELAYCTRL primitives are instantiated.
// Each instance has its own RST and RDY signal to allow for partial
// reconfiguration.
// The REFCLK signal is common to all instances
IDELAYCTRL dlyctrl_1 (
IDELAYCTRL dlyctrl_2 (
.
.
.
IDELAYCTRL dlyctrl_n (
// The user either declares the LOC constraints in the
// Verilog design file or in the following UCF file.
// Declaring LOC constraints in the Verilog file.
// synthesis attribute loc of dlyctrl_1 is "IDELAYCTRL_X0Y0";
// synthesis attribute loc of dlyctrl_2 is "IDELAYCTRL_X0Y1";
.
.
.
// synthesis attribute loc of dlyctrl_N is "IDELAYCTRL_XnYn";
// Declaring LOC constraints in the UCF file:
INST "dlyctrl_1" LOC=IDELAYCTRL_X0Y0;
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);
RST => rst_n
);
);
);
.RDY(rdy _1),
.REFCLK(refclk),
.RST(rst_1)
.RDY(rdy_2),
.REFCLK(refclk),
.RST(rst_2)
.RDY(rdy_n),
.REFCLK(refclk),
.RST(rst_n)
ILOGIC Resources
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