XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 153

• Manufacturer Part Number: XC4VFX12-10SFG363C
• Description: IC FPGA VIRTEX-4 FX 12K 363FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX12-10SFG363C

• Number Of Logic Elements/cells: 12312
• Number Of Labs/clbs: 1368
• Total Ram Bits: 663552
• Number Of I /o: 240
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 363-FBGA, FCBGA
• Package: 363FCBGA
• Family Name: Virtex®-4
• Device Logic Units: 12312
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 240
• Ram Bits: 663552
• For Use With: HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

FIFO Attributes
Table 4-12: FIFO16 Attributes
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Notes:
1. If FIFO16 is constrained to FIFO16_X#Y#, then RAMB16 can not be constrained to RAMB16_X#Y# since the same location would be
ALMOST_FULL_OFFSET
ALMOST_EMPTY_OFFSET
FIRST_WORD_FALL_THROUGH
DATA_WIDTH
LOC
used.
Attribute Name
FIFO ALMOSTEMPTY / ALMOSTFULL Flag Offset Range
R
Table 4-12
by setting the DATA_WIDTH attribute. The
has examples for setting the attributes.
The offset ranges for ALMOSTEMPTY and ALMOSTFULL are listed in
Table 4-13: FIFO ALMOSTFULL / EMPTY Flag Offset Range
The ALMOSTFULL and ALMOSTEMPTY offsets are usually set to a small value of less
than 10 to provide a warning that the FIFO is about to reach its limits. Since the full
capacity of any FIFO is normally not critical, most applications use the ALMOST_FULL
flag not only as a warning but also as a signal to stop writing.
Similarly, the ALMOST_EMPTY flag can be used to stop reading. However, this would
make it impossible to read the very last entries remaining in the FIFO. The user can ignore
the ALMOSTEMPTY signal and continue to read until EMPTY is asserted.
Notes:
1. ALMOST_EMPTY_OFFSET and ALMOST_FULL_OFFSET for any design must be less than the FIFO
4k x 4
2k x 9
1k x 18
512 x 36
Configuration
depth.
lists the FIFO16 attributes. The size of the asynchronous FIFO can be configured
12-bit
HEX
12-bit
HEX
Boolean
Integer
String
Type
See
See
FALSE,
TRUE
4, 9, 18, 36
Valid FIFO16
location
Standard
www.xilinx.com
5 to 4092
5 to 2044
5 to 1020
5 to 508
ALMOST_EMPTY_OFFSET
Table 4-13
Table 4-13
Values
FALSE
36
Default
“FIFO VHDL and Verilog Templates”
6 to 4093
6 to 2045
6 to 1021
6 to 509
FWFT
Setting determines ALMOST_FULL
condition. Must be set using
hexadecimal notation.
Setting determine ALMOST_EMPTY
condition. Must be set using
hexadecimal notation.
If TRUE, during a write of the 1st word
the word appears at the FIFO output
without RDEN asserted.
Sets the location of the FIFO16.
ALMOST_FULL_OFFSET
Notes
4 to 4091
4 to 2043
4 to 1019
4 to 507
Table
FIFO Attributes
4-13.
section
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