isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 109
isp1161bm
Manufacturer Part Number
isp1161bm
Description
Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1161BM.pdf
(137 pages)
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ISP1161BM
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Philips Semiconductors
9397 750 09567
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
BUSTATUS
EP14
EP6
23
15
R
R
R
0
0
7
0
reserved
Table 110: DcInterrupt register: bit description
Bit
31 to 24
23 to 10
9
8
7
6
5
4
3
2
1
0
EP13
EP5
22
14
R
R
R
0
0
6
0
Symbol
-
EP14 to EP1
EP0IN
EP0OUT
BUSTATUS
-
PSOF
SOF
EOT
SUSPND
RESUME
RESET
PSOF
EP12
EP4
21
13
R
R
R
0
0
5
0
Rev. 02 — 13 December 2002
EP11
Description
reserved
Logic 1 indicates the interrupt source(s): endpoint 14 to 1.
Logic 1 indicates the interrupt source: control IN endpoint.
Logic 1 indicates the interrupt source: control OUT endpoint.
Monitors the current USB bus status (0 = awake, 1 = suspend).
reserved
Logic 1 indicates that an interrupt is issued every 1 ms because
of the Pseudo SOF; after 3 missed SOFs ‘suspend’ state is
entered.
Logic 1 indicates that a SOF condition was detected.
Logic 1 indicates that an internal EOT condition was generated
by the DMA Counter reaching zero.
Logic 1 indicates that an ‘awake’ to ‘suspend’ change of state
was detected on the USB bus.
Logic 1 indicates that a ‘resume’ state was detected.
Logic 1 indicates that a bus reset condition was detected.
SOF
Full-speed USB single-chip host and device controller
EP3
20
12
R
R
R
0
0
4
0
EP10
EOT
EP2
19
11
R
R
R
0
0
3
0
SUSPND
EP9
EP1
18
10
R
R
R
0
0
2
0
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
RESUME
EP0IN
EP8
17
R
R
R
0
9
0
1
0
ISP1161
EP0OUT
RESET
109 of 137
EP7
16
R
R
R
0
8
0
0
0
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