isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 44
isp1161bm
Manufacturer Part Number
isp1161bm
Description
Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1161BM.pdf
(137 pages)
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Philips Semiconductors
10. HC registers
9397 750 09567
Product data
The HC contains a set of on-chip control registers. These registers can be read or
written by the Host Controller Driver (HCD). The Control and Status register sets,
Frame Counter register sets, and Root Hub register sets are grouped under the
category of HC Operational registers (32 bits). These operational registers are made
compatible to OpenHCI (Host Controller Interface) Operational registers. This makes
a provision that the OpenHCI HCD can be ported to ISP1161 easily.
Reserved bits may be defined in future releases of this specification. To ensure inter
operability, the HCD that does not use a reserved field must not assume that the
reserved field contains logic 0. Furthermore, the HCD must always preserve the
values of the reserved field. When a R/W register is modified, the HCD must first read
the register, modify the bits desired, and then write the register with the reserved bits
still containing the read value. Alternatively, the HCD can maintain an in-memory
copy of previously written values that can be modified and then written to the HC
register. When a write to set or clear the register is written, bits written to reserved
fields must be logic 0.
As shown in
these Operational registers (the 32-bit registers) are similar to those defined in the
OHCI specification, however, the addresses are equal to offset divided by 4.
Table
Rev. 02 — 13 December 2002
7, the offset locations (the commands for reading registers) of
Full-speed USB single-chip host and device controller
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
ISP1161
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