isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 17

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
acknowledge to ISP1161 via the DACK pin (DACK1 for HC and DACK2 for DC), and
at the same time, do the DMA transfer through the data bus. In the DMA mode, the
microprocessor must still issue a RD or WR signal to ISP1161’s RD or WR pin.
ISP1161 will repeat the DMA cycles until it receives an EOT signal to terminate the
DMA transfer.
ISP1161 supports both external EOT and internal EOT signals. The external EOT
signal is received as input from ISP1161’s EOT pin: it generally comes from the
external microprocessor. The internal EOT signal is generated by ISP1161 internally.
To select either, set the DcDMAConfiguration registers. For example, for the HC,
setting the DMACounterSelect bit of the HcDMAConfiguration register (21H - read,
A1H - write) to logic 1 will enable the DMA counter for DMA transfer. When the DMA
counter reaches the value of HcTransferCounter register, the internal EOT signal will
be generated to terminate the DMA transfer.
ISP1161 supports either single-cycle DMA operation or burst mode DMA operation.
In
HIGH and DACK is active LOW.
Fig 17. DMA transfer in single-cycle mode.
Figure 17
N = 1/2 byte count of transfer data.
RD or WR
D [ 15:0 ]
DREQ
DACK
EOT
and
Rev. 02 — 13 December 2002
Figure
data #1
18, the DMA transfer is configured such that DREQ is active
Full-speed USB single-chip host and device controller
data #2
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
data #N
ISP1161
MGT942
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