isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 18
isp1161bm
Manufacturer Part Number
isp1161bm
Description
Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1161BM.pdf
(137 pages)
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Philips Semiconductors
9397 750 09567
Product data
Fig 18. DMA transfer in burst mode.
N = 1/2 byte count of transfer data; K = number of cycles or burst.
RD or WR
D [ 15:0 ]
DREQ
DACK
EOT
data #1
8.6.1 Pin configuration
8.6 Interrupts
ISP1161 has separate interrupt request pins for USB HC (INT1) and USB DC (INT2).
The interrupt output signals have four configuration modes:
Mode 0
Mode 1
Mode 2
Mode 3
Figure 19
via the HcHardwareConfiguration register (see
to disable or enable the signals.
Fig 19. Interrupt pin operating modes.
data #K
shows these four interrupt configuration modes. They are programmable
Level trigger, active LOW (default at power-up)
Level trigger, active HIGH
Edge trigger, active LOW
Edge trigger, active HIGH.
data #(K 1)
Rev. 02 — 13 December 2002
INT
INT
INT
INT
Full-speed USB single-chip host and device controller
Mode 0 level triggered, active LOW
Mode 1 level triggered, active HIGH
Mode 2 edge triggered, active LOW
Mode 3 edge triggered, active HIGH
data #2K
166 ns
166 ns
INT active
INT active
INT active
INT active
data #(N K 1)
Section
clear or disable INT
clear or disable INT
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
10.4.1), which are also used
MGT944
data #N
ISP1161
MGT943
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