isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 12

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8. Microprocessor bus interface
9397 750 09567
Product data
7.6 GoodLink
8.1 Programmed I/O (PIO) addressing mode
8.2 DMA mode
Indication of a good USB connection is provided at pin GL through GoodLink
technology. During enumeration the LED indicator will blink on momentarily. When
the DC has been successfully enumerated (the device address is set), the LED
indicator will remain permanently on. Upon each successful packet transfer (with
ACK) to and from the ISP1161 the LED will blink off for 100 ms. During ‘suspend’
state the LED will remain off.
This feature provides a user-friendly indication of the status of the USB device, the
connected hub and the USB traffic. It is a useful field diagnostics tool for isolating
faulty equipment. It can therefore help to reduce field support and hotline overhead.
A generic PIO interface is defined for speed and ease-of-use. It also allows direct
interfacing to most microprocessors. To a microprocessor, the ISP1161 appears as a
memory device with a 16-bit data bus and uses only two address lines: A1 and A0 to
access the internal control registers and FIFO buffer RAM. Therefore, ISP1161
occupies only four I/O ports or four memory locations of a microprocessor. External
microprocessors can read or write ISP1161’s internal control registers and FIFO
buffer RAM through the programmed I/O (PIO) operating mode.
programmed I/O interface between a microprocessor and ISP1161.
The ISP1161 also provides DMA mode for external microprocessors to access its
internal FIFO buffer RAM. Data can be transferred by DMA operation between a
microprocessor’s system memory and ISP1161’s internal FIFO buffer RAM.
Remark: The DMA operation must be controlled by the external microprocessor
system’s DMA controller (Master).
Figure 9
ISP1161 provides two DMA channels:
Fig 8. Programmed I/O interface between microprocessor and ISP1161.
shows the DMA interface between a microprocessor system and ISP1161.
Rev. 02 — 13 December 2002
PROCESSOR
MICRO-
Full-speed USB single-chip host and device controller
D [ 15:0 ]
IRQ1
IRQ2
WR
RD
CS
A2
A1
P bus I/F
D [ 15:0 ]
RD
WR
CS
A1
A0
INT1
INT2
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
ISP1161
Figure 8
MGT933
ISP1161
shows the
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