isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 42
isp1161bm
Manufacturer Part Number
isp1161bm
Description
Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1161BM.pdf
(137 pages)
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Philips Semiconductors
9397 750 09567
Product data
Fig 36. Using external OC detection circuit.
Fig 37. ISP1161 suspend and resume clock scheme.
V BUS
REGULATOR
VOLTAGE
downstream
connector
XOSC
9.9.1 HC suspended state
USB
port
9.9 Suspend and wake-up
On
On
OC detect
V o
external
The HC can be put into suspended state by setting the HcControl register (01H -
read, 81H - write). See
XOSC_6MHz
(to DC PLL)
OC
EN
V i
DC_EnableClock
47 pF
(2 )
5 V
22
22
On
3.3 V or 5 V
V CC
H_PSWn
Rev. 02 — 13 December 2002
H_OCn
HC PLL
PLL_ClkOut
H_DMn
H_DPn
PLL_Lock
HC_EnableClock
Figure 23
Full-speed USB single-chip host and device controller
HC_RawClk48M
OC detect
regulator
bit 11 (SuspendClkNotStop)
HC_ClkOk
for the HC’s flow of USB states changes.
15 k
(2 )
bit 12
H_Wakeup (pin)
HcHardware Configuration
Configuration
HcHardware
ATX
DIGITAL
SWITCH
CLOCK
OC select
1
0 Reg
PSW
On
C/L
HC CORE
HC_Clk48MOut
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
HC_NeedClock
ISP1161
SIE
Configuration
HcHardware
CS (pin)
bit 10
MGT961
CORE
ISP1161
MGT958
HC
42 of 137
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