isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 31

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
9.4.2 Data organization
PTD data is used for every data transfer between a microprocessor and the USB bus,
and the PTD data resides in the buffer RAM. For an OUT or SETUP transfer, the
payload data is placed just after the PTD, after which the next PTD is placed. For an
IN transfer, some RAM space is reserved for receiving a number of bytes that is equal
to the total bytes of the transfer. After this, the next PTD and its payload data are
placed (see
Remark: The PTD is defined for both ATL and ITL type data transfer. For ITL, the
PTD data should be put into ITL buffer RAM, the ISP1161 takes care of the
Ping-Pong action for the ITL buffer RAM access.
The PTD data (PTD header and its payload data) is a structure of Dword (double-
word or 4 bytes) alignment. This means that the memory address is organized in
steps of 4 bytes. Therefore, the first byte of every PTD and the first byte of every
payload data are located at an address which is a multiple of 4.
an example in which the first payload data is 14 bytes long, meaning that the last byte
of the payload data is at the location 15H. The next addresses (16H and 17H) are not
multiples of 4. Therefore, the first byte of the next PTD will be located at the next
multiple-of-four address: 18H.
Fig 27. Buffer RAM data organization.
Figure
Rev. 02 — 13 December 2002
27).
bottom
Full-speed USB single-chip host and device controller
top
payload data of OUT transfer
payload data of OUT transfer
empty space for IN total data
PTD of OUT transfer
PTD of OUT transfer
PTD of IN transfer
RAM buffer
MGT952
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
000H
7FFH
Figure 28
ISP1161
illustrates
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