isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 112

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
Fig 48. Oscillator and LazyClock logic.
Fig 49. CLKOUT signal timing at ‘suspend’ and ‘resume’ for device controller.
If enabled, the 100 kHz 50% LazyClock frequency will be output on pin CLKOUT during ‘suspend’ state.
D_SUSPEND
D_WAKEUP
configuration
CKDIV [ 3:0 ]
GOSUSP
CLKOUT
hardware
CLKRUN
NOLAZY
register
.
.
.
.
.
.
SUSPEND
When ISP1161’s DC enters ‘suspend’ state (by setting and clearing bit GOSUSP in
the DcMode register), outputs D_SUSPEND and CLKOUT change state after
approximately 2 ms delay. When NOLAZY = 0 the clock signal on output CLKOUT
does not stop, but changes to the 100 kHz
When resuming from ‘suspend’ state by a positive pulse on input D_WAKEUP, output
SUSPEND is cleared and the clock signal on CLKOUT restarted after a 0.5 ms delay.
The timing of the CLKOUT signal at ‘suspend’ and ‘resume’ is given in
1.8 to 2.2 ms
XTAL OSC
Rev. 02 — 13 December 2002
4
enable
6 MHz
Full-speed USB single-chip host and device controller
LAZYCLOCK
PLL 8
enable
enable
48 MHz
100 (±50%) kHz
50% LazyClock frequency.
0.5 ms
(N + 1)
N
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
PLL circuit stable
MGS775
3 to 4 ms
0
1
NOLAZY
CLKOUT
ISP1161
004aaa038
Figure
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49.