isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 62

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 34:
9397 750 09567
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcRhPortStatus[1:2] register: bit allocation
31
23
15
0
7
0
implemented with special write behavior. If a transaction (token through handshake)
is in progress when a write to change port status occurs, the resulting port status
change must be postponed until the transaction completes. Reserved bits should
always be written logic 0.
Code (Hex): [1] = 15, [2] = 16 — read
Code (Hex): [1] = 95, [2] = 96 — write
reserved
reserved
Table 35:
Bit
31 to 21
20
19
R/W
R/W
30
22
14
0
6
0
HcRhPortStatus[1:2] register: bit description
Symbol
-
PRSC
OCIC
29
21
13
0
5
0
Rev. 02 — 13 December 2002
reserved
R/W
0
Description
reserved
PortResetStatusChange: This bit is set at the end of the 10 ms
port reset signal. The HCD writes logic 1 to clear this bit. Writing
logic 0 has no effect.
0 — port reset is not complete
1 — port reset is complete
PortOverCurrentIndicatorChange: This bit is valid only if
overcurrent conditions are reported on a per-port basis. This bit is
set when Root Hub changes the PortOverCurrentIndicator bit. The
HCD writes logic 1 to clear this bit. Writing logic 0 has no effect.
0 — no change in PortOverCurrentIndicator
1 — PortOverCurrentIndicator has changed
PRSC
PRS
Full-speed USB single-chip host and device controller
R/W
R/W
28
20
12
0
4
0
reserved
00H
R/W
OCIC
POCI
R/W
R/W
27
19
11
0
3
0
PSSC
PSS
R/W
R/W
26
18
10
0
2
0
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
PESC
LSDA
R/W
R/W
PES
R/W
25
17
0
9
0
1
0
ISP1161
CSC
CCS
PPS
R/W
R/W
R/W
62 of 137
24
16
0
8
0
0
0