isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 16

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
Fig 16. ISP1161’s internal FIFO buffer RAM access cycle.
write command
(16 bits)
8.4 FIFO buffer RAM by PIO mode
8.5 FIFO buffer RAM by DMA mode
Since ISP1161’s internal memory is structured as a FIFO buffer RAM, the FIFO buffer
RAM is mapped to dedicated register fields. Therefore, accessing ISP1161’s internal
FIFO buffer RAM is just like accessing the internal control registers in multiple data
phases.
Figure 16
a write cycle, the microprocessor first writes the FIFO buffer RAM’s command code to
the command port, and then writes the data words one by one to the data port until
half of the transfer’s byte count is reached. The HcTransferCounter register (22H -
read, A2H - write) is used to specify the byte count of a FIFO buffer RAM’s read cycle
or write cycle. Every access cycle must be in the same access direction. The read
cycle procedure is similar to the write cycle.
For ISP1161 DC’s FIFO buffer RAM access, see
The DMA interface between a microprocessor and ISP1161 is shown in
When doing a DMA transfer, at the beginning of every burst the ISP1161 outputs a
DMA request to the microprocessor via the DREQ pin (DREQ1 for HC and DREQ2
for DC). After receiving this signal, the microprocessor will reply with a DMA
Fig 15. Accessing ISP1161 DC control registers.
WR
RD
CS
D [ 15:0 ]
A1, A0
shows a complete access cycle of ISP1161’s internal FIFO buffer RAM. For
FIFO buffer RAM access cycle (transfer counter = 2N)
read/write data
#1 (16 bits)
Rev. 02 — 13 December 2002
DC command
write
code
11
Full-speed USB single-chip host and device controller
read/write data
#2 (16 bits)
DC register data
(lower word)
write
write
read
read
10
Section
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
read/write data
11.
#N (16 bits)
DC register data
(upper word)
write
write
read
read
10
ISP1161
MGT941
Figure
t
16 of 137
MGT940
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