isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 32

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
9.4.3 Operation and C program example
Figure 29
mode. ISP1161 provides one register as the access port for each buffer RAM. For the
ITL buffer RAM, the access port is the ITLBufferPort register (40H - read, C0H -
write). For the ATL buffer RAM, the access port is the ATLBufferPort register (41H -
read, C1H - write). The buffer RAM is an array of bytes (8 bits) while the access port
is a 16-bit register. Therefore, each read/write operation on the port accesses two
consecutive memory locations, incrementing the pointer of the internal buffer RAM by
two.
The lower byte of the access port register corresponds to the data byte at the even
location of the buffer RAM, and the higher byte in the access port register
corresponds to the other data byte at the odd location of the buffer RAM. Regardless
of the number of data bytes to be transferred, the command code must be issued
merely once, and it will be followed by a number of accesses of the data port (see
Section
When the pointer of the buffer RAM reaches the value of the HcTransferCounter
register, an internal EOT signal will be generated to set bit 2 (AllEOTInterrupt) of the
Hc PInterrupt register and update the HcBufferStatus register, to indicate that the
whole data transfer has been completed.
For ITL buffer RAM, every start of frame (SOF) signal (1 ms) will cause toggling
between ITL0 and ITL1 but this depends on the buffer status. If both ITL0BufferFull
and ITL1BufferFull of the HcBufferStatus register are already logic 1, meaning that
both ITL0 and ITL1 buffer RAMs are full, the toggling will not happen. In this case, the
microprocessor will always have access to ITL1.
Fig 28. PTD data with Dword alignment in buffer RAM.
8.4).
shows the block diagram for internal FIFO buffer RAM operations by PIO
Rev. 02 — 13 December 2002
Full-speed USB single-chip host and device controller
top
payload data
payload data
RAM buffer
(14 bytes)
(8 bytes)
(8 bytes)
PTD
PTD
MGT953
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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