isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 51

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 16:
9397 750 09567
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptEnable register: bit allocation
reserved
MIE
31
23
15
0
7
0
10.1.6 HcInterruptDisable register (R/W: 05H/85H)
Table 17:
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
Bit
31
30 to 7
6
5
4
3
2
1
0
RHSC
30
22
14
0
6
0
HcInterruptEnable register: bit description
Symbol
MIE
-
RHSC
FNO
UE
RD
SF
-
SO
FNO
29
21
13
0
5
0
Rev. 02 — 13 December 2002
Description
MasterInterruptEnable by the HCD: Logic 0 is ignored by the HC.
Logic 1 enables interrupt generation by events specified in other
bits of this register.
reserved
0 — ignore
1 — enable interrupt generation due to Root Hub Status Change
0 — ignore
1 — enable interrupt generation due to Frame Number Overflow
0 — ignore
1 — enable interrupt generation due to Unrecoverable Error
0 — ignore
1 — enable interrupt generation due to Resume Detect
0 — ignore
1 — enable interrupt generation due to Start of frame
reserved
0 — ignore
1 — enable interrupt generation due to Scheduling Overrun
Full-speed USB single-chip host and device controller
UE
28
20
12
0
4
0
reserved
reserved
R/W
00H
R/W
00H
R/W
R/W
reserved
RD
27
19
11
0
3
0
SF
26
18
10
0
2
0
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
reserved
25
17
0
9
1
0
ISP1161
51 of 137
SO
24
16
0
8
0
0