isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 68

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 40:
9397 750 09567
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcTransferCounter register: bit allocation
15
0
7
0
10.4.3 HcTransferCounter register (R/W: 22H/A2H)
Table 39:
This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer,
the number of bytes being read or written to the Isochronous Transfer List (ITL) or
Acknowledged Transfer List (ATL) buffer RAM must be written into this register. For a
DMA transfer, the number of bytes must be written into this register as well. However,
for this counter to be read into the DMA counter, the HCD must set bit 2
(DMACounterSelect) of the HcDMAConfiguration register. The counter value for ATL
must not be greater than 1000H, and for ITL it must not be greater than 800H. When
the byte count of the data transfer reaches this value, the HC will generate an internal
EOT signal to set bit 2 (AllEOTInterrupt) of the Hc PInterrupt register, and also
update the HcBufferStatus register.
Code (Hex): 22 — read
Code (Hex): A2 — write
Bit
6 to 5
4
3
2
1
0
14
0
6
0
Symbol
BurstLen[1:0] 00 — single-cycle burst DMA
DMAEnable
-
DMACounter
Select
ITL_ATL_
DataSelect
DMARead
WriteSelect
HcDMAConfiguration register: bit description
13
0
5
0
Rev. 02 — 13 December 2002
Description
01 — 4-cycle burst DMA
10 — 8-cycle burst DMA
11 — reserved
0 — DMA is terminated
1 — DMA is enabled; this bit will be reset to zero when DMA
transfer is completed
reserved
0 — DMA counter not used. External EOT must be used
1 — Enables the DMA counter for DMA transfer. The
HcTransferCounter register must be filled with non-zero values for
DREQ1 to be raised after bit DMA Enable is set
0 — ITL buffer RAM selected for ITL data
1 — ATL buffer RAM selected for ATL data
0 — read from ISP1161 HC’s FIFO buffer RAM
1 — write to ISP1161 HC’s FIFO buffer RAM
Full-speed USB single-chip host and device controller
12
0
4
0
Counter value
Counter value
R/W
R/W
11
0
3
0
10
0
2
0
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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9
0
1
0
ISP1161
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8
0
0
0