isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 94

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 76:
[1]
[2]
[3]
[4]
[5]
[6]
Table 77:
9397 750 09567
Product data
Name
Read Endpoint n Error Code
(n = 1 to 14)
Unlock Device
Write/Read DcScratch register
Read Frame Number
Read Chip ID
Read DcInterrupt register
Bit
Symbol
Reset
Access
With N representing the number of bytes; the number of words for 16-bit bus width is: (N + 1)/2.
During isochronous transfer in 16-bit mode, because N
Validating an OUT endpoint buffer causes unpredictable behavior of ISP1161’s DC.
Clearing an IN endpoint buffer causes unpredictable behavior of ISP1161’s DC.
Reads a copy of the Status register: executing this command does not clear any status bits or interrupt bits.
When accessing an 8-bit register in 16-bit mode, the upper byte is invalid.
Command and register summary
DcEndpointConfiguration register: bit allocation
FIFOEN
R/W
7
0
13.1.1 DcEndpointConfiguration (R/W: 30H–3FH/20H–2FH)
13.1 Initialization commands
Initialization commands are used during the enumeration process of the USB
network. These commands are used to configure and enable the embedded
endpoints. They also serve to set the USB assigned address of ISP1161’s DC and to
perform a device reset.
This command is used to access the DcEndpointConfiguration register of the target
endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction
(OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The
register bit allocation is shown in
The allocation of FIFO memory only takes place after all 16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have fixed configurations, they must be included in the initialization
sequence and be configured with their default values (see
allocation starts when endpoint 14 has been configured.
Remark: If any change is made to an endpoint configuration which affects the
allocated memory (size, enable/disable), the FIFO memory contents of all endpoints
becomes invalid. Therefore, all valid data must be removed from enabled endpoints
before changing the configuration.
Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 word
EPDIR
R/W
6
0
Destination
DcErrorCode register
endpoint 1 to 14
all registers with write access
DcScratch register
DcFrameNumber register
DcChipID register
DcInterrupt register
DBLBUF
R/W
…continued
5
0
Rev. 02 — 13 December 2002
1023, the firmware must take care of the upper byte.
FFOISO
Full-speed USB single-chip host and device controller
R/W
4
0
Table
77. A bus reset will disable all endpoints.
R/W
3
0
Code (Hex) Transaction
A2 to AF
B0
B2/B3
B4
B5
C0
R/W
2
0
read 1 word
write 1 word
write/read 1 word
read 1 word
read 1 word
read 2 words
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
FFOSZ[3:0]
Table
66). Automatic FIFO
R/W
[1]
[6]
1
0
ISP1161
R/W
94 of 137
0
0