isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 134

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
23. Revision history
Table 129: Revision history
9397 750 09567
Product data
Rev Date
02
20021213
CPCN
-
Description
Product data (9397 750 09567)
Modifications:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Added USB-IF certified logo.
Changed USB compliance from USB 1.1 to USB 2.0. Also, added the data rates.
Host Controller (HC) is adapted from Open Host Controller Interface Specification for
USB, release 1.0a .
Changed peer-to-peer to point-to-point.
Globally changed ISP1181 to ISP1181B.
Globally changed the DC register names to make them consistent with the HC register
names.
Globally removed references to PHP109.
Globally changed LazyClock value to 100 kHz 50%.
Section
Table
Section
Updated
Updated
Changed register values in:
Section
Table
Section
Section
Section
Section 11.2.1
Section
Section
Section
Section
Section 11.4.2
write protected.
Section 11.4.3
Section
Section
–
–
–
–
–
–
–
Table
Table
Table
Table
Table
Table
Table
2: updated description for pins 19, 24, 32, 33, 37, 38 and 40.
50: changed reset values.
2: removed the feature on ESD.
7.5: removed V
10.5.1: modified the chip ID.
10.6.1: added an example for clearer illustration.
11.1.1: updated the fifth list item.
11.1.2: updated the fifth list item.
11.2.1: Updated the content.
11.2.2: Updated the content.
11.3.6: removed “to both control endpoints” from the fourth sentence.
11.4.1: changed the content in ordered list item 5.
12: removed DACK2 from the list item “Programmable.....pins DREQ2 and EOT”.
12.2: removed EOP from the second sentence of the third paragraph.
21: added FSMaximumPacketSize to the FSMPS description.
28: NDP is now over bits 0 and 1 only and bits 13 to 15 are read only.
29: Changed description for OCPM and NOCP.
30: PPCM and DR now occupy only three bits, respectively.
32: added reset and access values for reserved bits; bit 17 symbol is OCIC.
34: LSDA reset is 0. Also, added reset and access values for the reserved bits.
36: changed reset value from 0 to1 for DREQOutputPolarity.
Section
Figure
Rev. 02 — 13 December 2002
and
fourth paragraph, first sentence: changed write-protected to read and
sixth item: added read-protected.
33,
8.6.
Section
Figure 35
SE
Full-speed USB single-chip host and device controller
from the remark.
11.2.2: switched titles.
and
Figure
36.
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
ISP1161
134 of 137