isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 36

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
9.5 HC’s operational model
Upon power up, the HCD sets up all operational registers (32 bits). The
FSLargestDataPacket field (bits 30 to 16) of the HcFmInterval register (0DH - read,
8DH - write) and the HcLSThreshold register (11H - read, 91H - write) determine the
end of the frame for full-speed and low-speed packets. By programming these fields,
the effective USB bus usage can be changed. Furthermore, the size of the ITL buffers
(HcITLBufferLength, 2AH - read, AAH - write) is programmed.
In the case when a USB frame contains both ISO and AT packets, two interrupts will
be generated per frame.
One interrupt is issued concurrently with the SOF. This interrupt (the ITLint is set in
the Hc PInterrupt register) triggers reading and writing of the ITL by the
microprocessor, after which the interrupt is cleared by the microprocessor.
Next the programmable AT Interrupt (the ATLint is set in the Hc PInterrupt register) is
issued, which triggers reading and writing of the ITL by the microprocessor, after
which the interrupt is cleared by the microprocessor. If the microprocessor cannot
handle the ISO interrupt before the next ISO interrupt, disrupted ISO traffic can result.
To be able to send more than one packet to the same Control or Bulk endpoint in the
same frame, an active bit and a ‘TotalBytes of transfer’ field are introduced (see
Table
(PTD) is transferred or if a transaction at that endpoint contained a fatal error. If all
PTD of the ATL are serviced once and the frame is not over yet, the HC starts looking
for a PTD with the active bit still set. If such a PTD is found and there is still enough
time in this frame, another transaction is started on the USB bus for this endpoint.
For ISO processing, the HCD has also to take care of the BufferStatus register (2CH
- read only) for the ITL buffer RAM operations. After the HCD writes ISO data into ITL
buffer RAM, the ITL0BufferFull or ITL1BufferFull bit (depends if it is ITL0 or ITL1) will
be set to logic 1.
After the HC processes the ISO data in the ITL buffer RAM then the corresponding
ITL0BufferDone or ITL1BufferDone bit will automatically be set to logic 1.
The HCD can clear the buffer status bits by a read of the ITL buffer RAM, and this
must be done within the 1 ms frame from which the ITL0BufferDone or
ITL1BufferDone was set. Failure to do so will cause the ISO processing to stop and a
power on reset or software reset will have to be applied to the HC.
For example, in the first frame, for the HCD doing a write of ISO-A data into the ITL0
buffer. This will cause the BufferStatus register to show that the ITL0 buffer is full by
setting the ITL0BufferFull bit to logic 1. At this stage the HCD cannot write ISO data
into the ITL0 buffer RAM again.
In the second frame, the Host Controller will process the ISO-A data in the ITL0
buffer. At the same time, the HCD can write ISO-B data into ITL1 buffer. When the
next SOF comes (the beginning of the third frame), both the ITL1BufferFull and
ITL0BufferDone are automatically set to logic 1.
In the third frame the HCD has to read ITL0 buffer at least two bytes (one word) to
clear both the ITL0BufferFull and ITL0BufferDone bits. If both are not cleared, when
the next SOF comes (the beginning of the fourth frame) the ITL0BufferDone bit will be
5). The active bit is cleared only if all data of the Philips Transfer Descriptor
Rev. 02 — 13 December 2002
Full-speed USB single-chip host and device controller
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
ISP1161
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