isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 83

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
Fig 38. DC typical suspend timing.
D_WAKEUP
GOSUSP
11.4.1 Suspend conditions
11.4 Suspend and resume
The ISP1161’s DC detects a USB ‘suspend’ status in the following cases:
With SoftConnect disabled, ISP1161 does not go into the ‘suspend’ state as long as
V
ISP1161’s DC will remain in ‘suspend’ state for at least 5 ms, before responding to
external wake-up events such as global resume, bus traffic, wake-up on CS or
WAKEUP. The typical timing is shown in
Bus-powered devices that are suspended must not consume more than 500 A of
current. This is achieved by shutting down the power to system components or
supplying them with a reduced voltage.
ISP1161’s DC is always in powered-off mode during ‘suspend’ state. Default,
bit PWROFF in the DcHardwareConfiguration register is logic 1 and this value should
not be changed under any condition. This powered-off mode is explained in detail in
Section
The steps leading up to ‘suspend’ status are as follows:
•
•
1. Upon detection of a ‘wake-up’ to ‘suspend’ transition ISP1161’s DC sets
2. When the firmware detects a ‘suspend’ condition it must prepare all system
3. In the interrupt service routine the firmware must check the current status of the
4. To meet the ‘suspend’ current requirements for a bus-powered device, the
BUS
A J-state is present on the USB bus for 3 ms
V
bit SUSPND in the DcInterrupt Register. This will generate an interrupt if
bit IESUSP in the DcInterruptEnable register is set.
components for ‘suspend’ state:
USB bus. When bit BUSTATUS in the DcInterrupt Register is logic 0, the USB
bus has left ‘suspend’ mode and the process must be aborted. Otherwise, the
next step can be executed.
internal clocks must be switched off by clearing bit CLKRUN in the
DcHardwareConfiguration register.
BUS
a. All signals connected to ISP1161’s DC must enter appropriate states to meet
b. All input pins of ISP1161’s DC must have a CMOS logic 0 or logic 1 level.
is present.
11.4.2.
the power consumption requirements of ‘suspend’ state.
is lost (weak pull-up or pull-down on D+ and D-).
Rev. 02 — 13 December 2002
suspend
>5 ms
Full-speed USB single-chip host and device controller
Figure
start detection of
wake-up conditions
38.
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
ISP1161
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