isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 96

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 81:
[1]
Table 83:
9397 750 09567
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
DcMode register: bit allocation
DcHardwareConfiguration register: bit allocation
reserved
DMAWD
R/W
R/W
0
15
7
0
[1]
13.1.4 DcHardwareConfiguration Register (R/W: BBH/BAH)
reserved
Table 82:
This command is used to access the DcHardwareConfiguration register, which
consists of 2 bytes. The first (lower) byte contains the device configuration and
control values, the second (upper) byte holds the clock control bits and the clock
division factor. The bit allocation is given in
of the programmed bit values.
The DcHardwareConfiguration register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA
operating mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB — write/read DcHardwareConfiguration register
Transaction — write/read 1 word
EXTPUL
Bit
7
6
5
4
3
2
1
0
R/W
R/W
14
6
0
0
DcMode register: bit description
Symbol
DMAWD
-
GOSUSP
-
INTENA
DBGMOD
-
SOFTCT
GOSUSP
NOLAZY
R/W
R/W
13
5
0
1
Rev. 02 — 13 December 2002
CLKRUN
reserved
Description
Logic 1 selects 16-bit DMA bus width (bus configuration
modes 0 and 2). Logic 0 selects 8-bit DMA bus width. Bus reset
value: unchanged.
reserved
Writing logic 1 followed by logic 0 will activate ‘suspend’ mode.
reserved
Logic 1 enables all interrupts. Bus reset value: unchanged; or
details, see
Logic 1 enables debug mode, where all NAKs and errors will
generate an interrupt. Logic 0 selects normal operation, where
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints).
Bus reset value: unchanged.
reserved
Logic 1 enables SoftConnect (see
ignored if EXTPUL = 1 in the DcHardwareConfiguration register
(see
Full-speed USB single-chip host and device controller
R/W
R/W
12
4
0
0
Table
83). Bus reset value: unchanged.
Section
INTENA
R/W
R/W
0
11
3
0
[1]
Table
8.6.3.
DBGMOD
83. A bus reset will not change any
R/W
R/W
0
10
2
0
[1]
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
CKDIV[3:0]
Section
reserved
R/W
R/W
0
7.5). This bit is
1
9
1
[1]
ISP1161
SOFTCT
R/W
R/W
96 of 137
0
0
8
1
[1]