isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 13

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
8.3.1 I/O port addressing
8.3 Control registers access by PIO mode
The EOT signal is an external end-of-transfer signal used to terminate the DMA
transfer. Some microprocessors may not have this signal. In this case, ISP1161
provides an internal EOT signal to terminate the DMA transfer as well. Setting the
HcDMAConfiguration register (21H - read, A1H - write) enables ISP1161’s HC
internal DMA counter for DMA transfer. When the DMA counter reaches the value
that is set in the HcTransferCounter (22H - read, A2H - write) register to be used as
the byte count of the DMA transfer, the internal EOT signal will be generated to
terminate the DMA transfer.
Table 3
address should include the chip select signal CS and the address lines A1 and A0.
However, the direction of the access of the I/O ports is controlled by the RD and WR
signals. When RD is LOW, the microprocessor reads data from ISP1161’s data port.
When WR is LOW, the microprocessor writes a command to the command port, or
writes data to the data port.
Table 3:
Figure 10
ISP1161’s internal control registers.
Port
0
1
2
3
•
•
Fig 9. DMA interface between microprocessor and ISP1161.
DMA channel 1 (controlled by DREQ1 and DACK1 signals) is for the DMA transfer
between a microprocessor’s system memory and ISP1161 HC’s internal FIFO
buffer RAM
DMA channel 2 (controlled by DREQ2 and DACK2 signals) is for the DMA transfer
between a microprocessor’s system memory and ISP1161 DC’s internal FIFO
buffer RAM
shows ISP1161’s I/O port addressing. Complete decoding of the I/O port
and
Pin CS
LOW
LOW
LOW
LOW
I/O port addressing
Figure 11
Rev. 02 — 13 December 2002
PROCESSOR
MICRO-
Pin A1
LOW
LOW
HIGH
HIGH
illustrate how an external microprocessor accesses
Full-speed USB single-chip host and device controller
DREQ1
DREQ2
DACK1
DACK2
D [ 15:0 ]
Pin A0
LOW
HIGH
LOW
HIGH
EOT
WR
RD
Access
R/W
W
R/W
W
P bus I/F
Data bus width Description
16 bits
16 bits
16 bits
16 bits
D [ 15:0 ]
RD
WR
DACK1
DREQ1
DACK2
DREQ2
EOT
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
ISP1161
MGT934
HC data port
HC command port
DC data port
DC command port
ISP1161
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