isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 54

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 22:
9397 750 09567
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcFmRemaining register: bit allocation
FRT
31
23
15
R
0
0
7
0
10.2.2 HcFmRemaining register (R: 0EH)
reserved
R
Table 21:
The HcFmRemaining register is a 14-bit down counter showing the bit time remaining
in the current frame.
Code (Hex): 0E — read
Bit
30 to 16
15 to 14
13 to 0
30
22
14
0
0
6
0
HcFmInterval register: bit description
Symbol
FSMPS
[14:0]
-
FI[13:0]
29
21
13
0
0
5
0
Rev. 02 — 13 December 2002
Description
FSLargestDataPacket (FSMaximumPacketSize): Specifies a
value which is loaded into the Largest Data Packet Counter at the
beginning of each frame. The counter value represents the largest
amount of data in bits which can be sent or received by the HC in a
single transaction at any given time without causing a scheduling
overrun. The field value is calculated by the HCD.
reserved
FrameInterval: Specifies the interval between two consecutive
SOFs in bit times. The nominal value is set to be 11999. The HCD
must store the current value of this field before resetting the HC.
By setting the HostControllerReset bit 0 field of
HcCommandStatus register will cause the HC to reset this field to
its nominal value. HCD may choose to restore the stored value
upon completing the Reset sequence.
Full-speed USB single-chip host and device controller
28
20
12
0
0
4
0
reserved
FR[7:0]
00H
R
R
reserved
27
19
11
R
0
0
3
0
FR[13:8]
R
…continued
26
18
10
0
0
2
0
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
25
17
0
9
0
1
0
ISP1161
54 of 137
24
16
0
8
0
0
0