isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 20

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
8.6.3 DC’s interrupt output pin (INT2)
the 6-input OR gate would output logic 1. This output is AND-ed with the value of MIE
(bit 31 of HcInterruptEnable). Logic 1 at the AND gate will cause bit OPR in the
Hc PInterrupt register to be set to logic 1.
Group 1 contains six possible interrupt events, one of which is the output of group 2
interrupt sources. The Hc PInterrupt and Hc PInterruptEnable registers work in the
same way as the HcInterruptStatus and HcInterruptEnable registers in the interrupt
group 2. The output from the 6-input OR gate is connected to a latch, which is
controlled by InterruptPinEnable (bit 0 of the HcHardwareConfiguration register).
In the event in which the software wishes to temporarily disable the interrupt output of
the ISP1161 Host Controller, the following procedure should be followed:
To re-enable the interrupt generation:
Remark: Bit InterruptPinEnable in the HcHardwareConfiguration register latches the
interrupt output. When this bit is set to logic 0, the interrupt output will remain
unchanged, regardless of any operations on the interrupt control registers.
If INT1 is asserted, and the Host Controller Driver (HCD) wishes to temporarily mask
off the INT signal without clearing the Hc PInterrupt register, the following procedure
should be followed:
To re-enable the interrupt generation:
The four configuration modes of DC’s interrupt output pin INT2 can also be
programmed by setting bits INTPOL and INTLVL of the DcHardwareConfiguration
Register (BBH - read, BAH - write). Bit INTENA of the DcMode Register (B9H - read,
B8H - write) is used to enable pin INT2.
interrupt events and pin INT2.
Each of the indicated USB events is logged in a status bit of the DcInterrupt register.
Corresponding bits in the DcInterruptEnable register determine whether or not an
event will generate an interrupt.
1. Make sure that bit InterruptPinEnable in the HcHardwareConfiguration register is
2. Clear all bits in the Hc PInterrupt register.
3. Set bit InterruptPinEnable to logic 0.
1. Set all bits in the Hc PInterrupt register.
2. Set bit InterruptPinEnable to logic 1.
1. Make sure that bit InterruptPinEnable is set to logic 1.
2. Clear all bits in the Hc PInterruptEnable register.
3. Set bit InterruptPinEnable to logic 0.
1. Set all bits in the Hc PInterruptEnable register according to the HCD
2. Set bit InterruptPinEnable to logic 1.
set to logic 1.
requirements.
Rev. 02 — 13 December 2002
Full-speed USB single-chip host and device controller
Figure 21
shows the relationship between the
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
ISP1161
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