isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 128

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
20.2 Interfacing a ISP1161 with a SH7709 RISC processor
This section shows a typical interface circuit between ISP1161 and a RISC
processor. The Hitachi SH-3 series RISC processor SH7709 is used as the example.
The main ISP1161 signals to be taken into consideration for connecting to a SH7709
RISC processor are:
Remark: SH7709’s system clock input is for reference only. Refer to SH7709’s
specification for its actual use.
ISP1161 can work under either 3.3 V or 5 V power supply; however, its internal core
actually works at 3.3 V. When using 3.3 V as the power supply input, the internal
DC/DC regulator will be bypassed. It is best to connect all four power supply pins
(V
Section
All of the ISP1161’s I/O pins are 5 V tolerant. This feature allows the ISP1161 the
flexibility to be used in an embedded system under either a 3.3 V or a 5 V power
supply.
A typical SH7709 interface circuit is shown in
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CC
A 16-bit data bus: D15 to D0 for ISP1161. ISP1161 is ‘little endian’ compatible.
Two address lines A1 and A0 are needed for a complete addressing of the
ISP1161 internal registers:
The CS line is used for chip selection of ISP1161 in a certain address range of the
RISC system. This signal is active LOW.
RD and WR are common read and write signals. These signals are active LOW.
There are two DMA channel standard control lines:
In each case one channel is used by the host controller and the other channel is
used by the device controller. These signals have programmable active levels.
Two interrupt lines: INT1 (used by the host controller) and INT2 (used by the
device controller). Both have programmable level/edge and polarity (active HIGH
or LOW).
The internal 15 k pull-down resistors are used for the HCs two USB downstream
ports.
The RESET signal is active LOW.
– A1 = 0 and A0 = 0 will select the Data Port of the Host Controller
– A1 = 0 and A0 = 1 will select the Command Port of the Host Controller
– A1 = 1 and A0 = 0 will select the Data Port of the Device Controller
– A1 = 1 and A0 = 1 will select the Command Port of the Device Controller
– DREQ1 and DACK1
– DREQ2 and DACK2
, V
reg(3.3)
14).
, V
hold1
Rev. 02 — 13 December 2002
and V
Full-speed USB single-chip host and device controller
hold2
) to the 3.3 V power supply (for more information see
Figure
64.
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
ISP1161
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