isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 19

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
Fig 20. HC interrupt logic.
HcInterruptEnable
HcInterruptStatus
register
register
RHSC
RHSC
FNO
FNO
MIE
RD
SO
RD
SO
UE
SF
UE
SF
8.6.2 HC’s interrupt output pin (INT1)
To program the four configuration modes of the HC’s interrupt output signal (INT1),
set bits InterruptPinTrigger and InterruptOutputPolarity of the
HcHardwareConfiguration register (20H - read, A0H - write). Bit InterruptPinEnable is
used as the master enable setting for pin INT1.
INT1 has many interrupt events, as shown in
The interrupt events of the Hc PInterrupt register (24H - read, A4H - write) changes
the status of pin INT1 when the corresponding bits of the Hc PInterruptEnable
register (25H - read, A5H - write) and pin INT1’s global enable bit (InterruptPinEnable
of the HcHardwareConfiguration register) are all set to enable status.
However, events that come from the HcInterruptStatus register (03H - read, 83H -
write) affect only the OPR_Reg bit of the Hc PInterrupt register. They cannot directly
change the status of pin INT1.
There are two groups of interrupts represented by group 1 and group 2 in
A pair of registers control each group.
Group 2 contains six possible interrupt events (recorded in the HcInterruptStatus
register). On occurrence of any of these events, the corresponding bit would be set to
logic 1; and if the corresponding bit in the HcInterruptEnable register is also logic 1,
group 2
OR
Rev. 02 — 13 December 2002
INT1
HcµPInterrupt
register
Full-speed USB single-chip host and device controller
LATCH
OR
Figure
LE
20.
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
HcµPInterruptEnable
HcHardwareConfiguration
register
InterruptPinEnable
register
ISP1161
Figure
MGT945
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20.