IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 100

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

6–2
SignalTap II Nodes
SignalTap II Trigger Conditions
SignalTap II Example Designs
DSP Builder Standard Blockset User Guide
f
4. Choose one of the JTAG cable ports in the Signal Compiler dialog box or the
5. Using Signal Compiler, synthesize your model, perform compilation in the
6. Specify the required trigger conditions in the SignalTap II Logic Analyzer
For details of the SignalTap II Logic Analyzer and SignalTap II Node
blocks, refer to the descriptions of these blocks in the AltLab Library chapter in the
Builder Standard Blockset Libraries
A node represents a wire carrying a signal that travels between different logical
components of a design file. The SignalTap II logic analyzer can capture signals from
any internal device node in a design file, including I/O pins.
The SignalTap II logic analyzer can analyze up to 128 internal nodes or I/O elements.
As more it capture more signals, it uses more logic elements (LEs) or embedded
system blocks (ESBs).
Before capturing signals, assign each node to analyze to a SignalTap II logic analyzer
input channel. To assign a node to an input channel, you must connect it to a
SignalTap II Node block.
The trigger pattern describes a logic event in terms of logic levels or edges. The
SignalTap II logic analyzer uses a comparison register to recognize the moment when
the input signals match the data specified in the trigger pattern.
The trigger pattern comprises a logic condition for each input signal. By default, all
signal conditions for the trigger pattern are set to Don’t Care, masking them from
trigger recognition. You can select one of the following logic conditions for each input
signal in the trigger pattern:
■
■
■
■
■
■
The SignalTap II logic analyzer triggers when it detects the trigger pattern on the
input signals.
Altera provides several example designs
SignalTap II Logic Analyzer dialog box.
Quartus II software, and download your design into the DSP development board
(starter or professional).
block.
Don’t care
Low
High
Rising edge
Falling edge
Either edge
Preliminary
section in volume 2 of the DSP Builder Handbook.
(Figure
Chapter 6: Performing SignalTap II Logic Analysis
6–1).
© June 2010 Altera Corporation
SignalTap II Example Designs
DSP