IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 135

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 8: Using Black Boxes for HDL Subsystems
HDL Import Design Example
© June 2010 Altera Corporation
Figure 8–3. Simulink Simulation Results for the Impulse Stimulus
6. Double-click on the manual switch connected to the Tsamp block to select the
7. Click Start on the Simulation menu in your model window.
8. Double-click on the Scope block to view the simulation results.
9. Press the Autoscale icon to resize the scope.
Figure 8–4. Simulink Simulation Results for the Chirp Stimulus
The HDL import tutorial is complete. You can optionally compile your model for
synthesis or perform RTL simulation on your design by following similar procedures
to those described in the
chirp_in stimulus—a sinusoidal signal the frequency of which increases at a linear
rate with time.
Figure 8–4
shows the simulation results.
“Getting
Preliminary
Started”.
DSP Builder Standard Blockset User Guide
8–5