IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 319

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 6: IO & Bus Library
Constant
Table 6–14. Constant Block Parameters (Part 2 of 2)
Table 6–15. Constant Block I/O Formats
Figure 6–9. Constant Block Example
© June 2010 Altera Corporation
Rounding Mode
Saturation Mode
Specify Clock
Clock
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
[L].[R]
Name
[LP].[RP]
Table
Simulink (2),
is an input port. O1
6–15:
Truncate,
Round Towards Zero,
Round Away From Zero,
Round To Plus Infinity,
Convergent Rounding
Wrap, Saturate
On or Off
User defined
(Parameterizable)
Table 6–15
Figure 6–9
(3)
[L].[R]
Value
is an output port.
O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0)
shows the Constant block I/O formats.
shows an example with the Constant block.
(Note 1)
The rounding mode. Refer to the description of the
information about the rounding modes.
The saturation mode.
Turn on to explicitly specify the clock name.
Specifies the name of the required clock signal.
Preliminary
VHDL
Description
DSP Builder Standard Blockset Libraries
Round
block for more
Type
Explicit
6–11
(4)