IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 38

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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Compiling the Design
DSP Builder Standard Blockset User Guide
4. Start simulation by clicking Start on the Simulation menu.
5. Double-click the Scope block to view the simulation results.
6. Click the Autoscale icon (binoculars) to auto-scale the waveforms.
Figure 2–9. Scope Simulation Results
To create and compile a Quartus II project for your DSP Builder design, and to
program your design onto an Altera FPGA, add a Signal Compiler block by
following these steps:
1. Select the AltLab library from the Altera DSP Builder Blockset folder in the
2. Drag and drop a Signal Compiler block into your model.
3. Double-click the Signal Compiler block in your model to display the Signal
4. Click Compile.
Figure 2–9
Simulink Library Browser.
Compiler dialog box
The dialog box allows you to set the target device family. For this tutorial, you can
use the default Stratix device family.
shows the scaled waveforms.
(Figure
Preliminary
2–10).
© June 2010 Altera Corporation
Chapter 2: Getting Started
Compiling the Design