IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 192

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

1–2
BP (Bus Probe)
Clock
DSP Builder Standard Blockset Libraries
1
The Bus Probe (BP) block is a sink, which you can place on any node of a model. The
Bus Probe block does not have any hardware representation and therefore does not
appear in the VHDL RTL representation generated by the
The Display in Symbol parameter selects the graphical shape of the symbol in your
model and the information that is reported there
Table 1–1. Bus Probe Block “Display in Symbol” Parameter
After simulating your model, the Bus Probe block back-annotates the following
information in the parameters dialog box for the Bus Probe block:
■
■
■
Use the Clock block in the top level of a design to set the base hardware clock
domain.
The block name is the name of the clock signal and must be a valid VHDL identifier.
A design can have zero or one base clock in a design and an error issues if you try to
use more than one base clock. You can specify the required units and enter any
positive value with the specified units. However, the clock period must be greater
than 1ps but less than 2.1ms.
If no base clock exists in your design, a default clock (clock) with a 20-ns real-world
period and a Simulink sample time of 1 is automatically created with a default Active
Low reset (aclr).
To avoid sample time conflicts in the Simulink simulation, ensure that the sample
time specified in the Simulink source block matches the sample time specified in the
Input block (driven by the Clock block or a derived clock).
Place additional clocks in the system by adding
Each clock must have a unique reset name. As all clock blocks have the same default
reset name (aclr) ensure you specify a valid unique name with multiple clocks.
You can add reset synchronizer circuitry for this clock domain by specifying the reset
type to be either synchronized active low or synchronized active high.
When you specify these reset types, DSP Builder adds two extra registers to avoid
metastability issues during reset removal.
Circle
Rectangle
Maximum value reached during simulation
Minimum value reached during simulation
Maximum number of integer bits required during simulation
Shape of
Symbol
Maximum number of integer bits required during simulation.
Maximum or minimum value reached during simulation.
Preliminary
Data Reported in Symbol
Clock_Derived
(Table
1–1).
Signal Compiler
© June 2010 Altera Corporation
blocks.
Chapter 1: AltLab Library
BP (Bus Probe)
block.