IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 155

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Figure 11–1. FIFO Design Example Top-Level Schematic
© June 2010 Altera Corporation
1
This chapter describes how to implement a state machine in DSP Builder.
The State Machine Table block is not available on Linux and is deprecated on
Windows. Use the State Machine Editor block in new designs.
The design example, fifo_control_logic.mdl, contains a simple state machine to
implement the control logic for a first-in first-out (FIFO) memory structure.
The design files for this example are in the <DSP Builder install path>\
DesignExamples\Tutorials\StateMachine\StateMachineTable directory.
Figure 11–1
The state machine in this design example feeds the control inputs of a Dual-Port
RAM block and the inputs of an address counter.
The state machine has the following operation:
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■
■
■
When you assert the push input and the address counter is less than 250, the
address counter increments and a byte of data writes to memory.
When you assert the pop input and the address counter is greater than 0, the
address counter decrements and a byte of data reads from memory.
When the address counter is equal to 0, the empty flag asserts
When the address counter is equal to 250, the full flag asserts.
shows the top-level schematic for the FIFO design example.
11. Using the State Machine Library
Preliminary
DSP Builder Standard Blockset User Guide