IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 254

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–8
Complex Constant
Table 3–10. Complex Constant Block Parameters
Table 3–11. Complex Constant Block I/O Formats
Figure 3–4. Complex Constant Block Example
DSP Builder Standard Blockset Libraries
Real Part
Imaginary Part
Bus Type
[number of bits].[] >= 0
[].[number of bits] >= 0
Specify Clock
Clock
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
[L].[R]
Name
Real([L1].[R1])Imag([L1].[R1])
Table
Simulink (2),
is an input port. O1
3–11:
User Defined
User Defined
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
(Parameterizable)
On or Off
User defined
The Complex Constant block outputs a fixed-point complex constant value.
Table 3–10
Table 3–11
Figure 3–4
Complex AddSub block.
(3)
[L].[R]
Value
is an output port.
O1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
O1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
shows the Complex Constant block I/O formats.
shows the Complex Constant block parameters.
shows an example with Complex Constant blocks as inputs to a
Specify the value of the real part of the constant.
Specify the value of the imaginary part of the constant.
Specify the number format of the bus.
Specify the number of bits to the left of the binary point, including the sign bit.
This parameter does not apply to single-bit buses.
Specify the number of bits to the right of the binary point. This parameter
applies only to signed fractional buses.
Turn on to explicitly specify the clock name.
Specify the clock signal name.
(Note 1)
Preliminary
VHDL
Description
Chapter 3: Complex Type Library
© June 2010 Altera Corporation
Explicit
Complex Constant
Type
(4)