IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 206

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

1–16
Table 1–18. Subsystem Builder Block Parameters
DSP Builder Standard Blockset Libraries
Select HDL File
Build SubSystem
Name
User defined Browse for the VHDL or Verilog HDL file to import.
The Subsystem Builder block automatically maps any input ports named
simulink_clock in the VHDL entity section to the global VHDL clock signal, and
maps any input ports named simulink_sclr in the VHDL entity section to the
global VHDL synchronous clear signal.
The VHDL entity should be formatted according to the following guidelines:
■
■
■
■
■
The Verilog HDL module should be formatted according to the following guidelines:
■
■
■
■
To use the Subsystem Builder block, drag and drop it into your model, click
Select HDL File, specify the file to import, and click Build.
Table 1–18
Value
—
The VHDL file should contain a single entity
Port direction: in or out
Port type: STD_LOGIC or STD_LOGIC_VECTOR
Bus size:
■
■
■
Single port declaration per line:
■
■
The Verilog HDL file should contain a single module
Port direction: input or output
Bus size:
■
■
■
Single port declaration per line:
■
■
a(7 DOWNTO 0) is supported (0 is the LSB, and must be 0)
a(8 DOWNTO 1) is not supported
a(0 TO 7) is not supported
a:STD_LOGIC; is supported
a,b,c:STD_LOGIC; is not supported
input [7:0] a; is correct (0 is the LSB, and must be 0)
input [8:1] a; is not supported
input [0:7] a; is not supported
input [7:0] a; is correct
input [7:0] a,b,c; is not supported
Click to build a subsystem for the selected HDL file.
shows the Subsystem Builder block parameters.
Preliminary
Description
© June 2010 Altera Corporation
Chapter 1: AltLab Library
Subsystem Builder