IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 230

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–22
Table 2–33. Multiplier Block Parameters
DSP Builder Standard Blockset Libraries
Bus Type
Input [number of bits].[]
Input [].[number of bits]
Number of Pipeline Stages
Both Inputs Have Same Bit
Width
Input b [number of bits].[]
Input b [].[number of bits]
Full Resolution for Output
Result
Output MSB
Output LSB
Output [number of bits].[]
Output [].[number of bits]
Use Dedicated Circuitry
Use Enable Port
Use Asynchronous Clear
Port
Name
Table 2–33
Table 2–34
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0
(Parameterizable)
>= 0
(Parameterizable)
>= 0
(Parameterizable)
On or Off
>= 0
(Parameterizable)
>= 0
(Parameterizable)
On or Off
>= 0
(Parameterizable)
>= 0
(Parameterizable)
>= 0
(Parameterizable)
>= 0
(Parameterizable)
AUTO, YES, NO
On or Off
On or Off
Value
lists the parameters for the Multiplier block.
shows the Multiplier block I/O formats.
The bus number format to use for the Multiplier block.
Specify the number of bits to the left of the binary point for input a (or
both input signals if set to have the same width).
Specify the number of bits to the right of the binary point for input a (or
both input signals if set to have the same width). This option applies only
to signed fractional formats.
The number of pipeline stages. The ena and aclr ports are available
only if the block is registered (that is, if the number of pipeline stages is
greater than or equal to 1).
Turn on if you want input a and input b to have the same bit width. When
off, additional fields are available to specify the number of bits to the left
and right of the binary point for input b.
Specify the number of bits to the left of the binary point for input b.
Specify the number of bits to the right of the binary point for input b. This
option applies only to signed fractional formats.
When on, the multiplier output bit width is full resolution. When off, you
can specify the number of bits for the output.
Specify the number of MSBs in the output for an integer bus.
Specify the number of LSBs in the output for an integer bus.
Specify the number of bits to the left of the binary point for the output r.
This option applies only to signed fractional formats.
Specify the number of bits to the left of the binary point for the output r.
This option applies only to signed fractional formats.
Use dedicated multiplier circuitry (if supported by your target device). A
value of AUTO means that the Quartus II software uses the dedicated
multiplier circuitry based on the width of the multiplier.
Turn on to use the clock enable input (ena).
Turn on to use the synchronous clear input (aclr).
Preliminary
Description
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Multiplier