IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 351

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 9: Storage Library
LUT (Look-Up Table)
Table 9–15. FIFO Block I/O Formats
Figure 9–5. FIFO Block Example
LUT (Look-Up Table)
© June 2010 Altera Corporation
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
I4
O1
O2
O3
O4
[L].[R]
[L1].[R1]
[1]
[1]
[1]
[L1].[R1]
[1]
[1]
[L2].[0]
Table
Simulink (2),
is an input port. O1
9–15:
1
Table 9–15
Figure 9–5
The LUT (Look-Up Table) block stores data as 2
table. The values of the words are specified in the data vector field as a MATLAB
array.
Depending on the look-up table size, the synthesis tool may use logic cells or
embedded array blocks (EABs), embedded system blocks (ESBs), or TriMatrix
memory.
If you want to use a .hex to store data, use the
(3)
[L].[R]
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC
I3: in STD_LOGIC
I4: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O2: out STD_LOGIC
O3: out STD_LOGIC
O4: out STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0)
shows the FIFO block I/O formats.
shows an example with the FIFO block.
(Note 1)
Preliminary
VHDL
ROM
(address width)
block not the LUT block.
DSP Builder Standard Blockset Libraries
words of data in a look-up
™
Type
Explicit
Explicit
9–11
(4)