IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 66

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–22
Create Black Box and HDL Import
Using a MATLAB Array or .hex File to Initialize a Block
Comparison Utility
Adding Comments to Blocks
DSP Builder Standard Blockset User Guide
f
You can add your own VHDL or Verilog HDL code to your design and specify which
subsystem block(s) DSP Builder should translate into VHDL. You can implement this
process—creating a black box—implicitly or explicitly.
An explicit black box uses the HDL Input, HDL Output, HDL Entity, and
Subsystem Builder blocks. For information about using these blocks to create an
explicit black box, refer to
An implicit black box uses the HDL Import block to instantiate the black-box
subsystem. For information about creating an implicit black box with your own HDL
code, refer to the
Use a MATLAB array to specify the values entered in the LUT block or to initialize the
Dual-Port RAM, Single-Port RAM, True Dual-Port RAM, or ROM blocks. You
can also use an Intel format hexadecimal format (.hex) file to initialize a RAM or ROM
block.
If the MATLAB array data values or the values in the .hex file do not represent exactly
in the selected data type, DSP Builder rounds them and issues a warning. DSP Builder
rounds the values by expressing the number in binary format, then truncates to the
specified width, which results in rounding towards minus infinity.
For example, if the input value is –0.25 (minimally expressed in signed binary
fractional two’s compliment format as 111) and the selected target data format is
signed fractional [1].[1], DSP Builder truncates the value to 11 = –0.5. DSP
Builder rounds the value towards minus infinity to the nearest representable number.
Similarly, if you select unsigned integer data type and the value is 1.9, DSP Builder
rounds this value down to 1.
DSP Builder provides a simple utility that runs simulation comparison between
Simulink and ModelSim from the command line:
A testbench GUI displays messages as DSP Builder performs the comparison. The
command returns true (1) or false (0) according to whether the simulation results
match and the output is recorded in the specified log file.
For more information about running a comparison between Simulink and ModelSim,
refer to
You can add comments to any DSP Builder block by right-clicking on the block to
display the Block Properties dialog box and entering text in the Description field of
the dialog box
alt_dspbuilder_verifymodel('modelname.mdl', 'logfile.txt')r
“Performing RTL Simulation”
(Figure 3–21 on page
“HDL Import Design Example”
“Subsystem Builder Design Example”
Preliminary
3–23).
in
Chapter
in
2.
Chapter
Chapter 3: Design Rules and Procedures
8.
© June 2010 Altera Corporation
Create Black Box and HDL Import
in
Chapter
8.