IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 212

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–4
Table 2–5. Bit Level Sum of Products Block Parameters
Table 2–6. Bit Level Sum of Products Block I/O Formats
DSP Builder Standard Blockset Libraries
Number of Coefficients 1–8
Coefficient Number of
Bits
Signed Integer
Fixed-Coefficient
Values
Register Inputs
Use Enable Port
Use Synchronous
Clear Port
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
...
Ii
...
In
I(n+1)
I(n+2)
O1
[L].[R]
[1].[0]
[1].[0]
[1].[0]
[L0].[0]
Table
Simulink (2),
Name
is an input port. O1
[1]
[1]
2–6:
(3)
Table 2–4. Bit Level Sum of Products Block Inputs and Outputs
Table 2–5
Table 2–6
a(0) to a(n–1) Input
ena
sclr
q
>= 1–51
(Parameterizable)
User Defined
(Parameterizable)
On or Off
On or Off
On or Off
[L].[R]
I1: in STD_LOGIC
...
Ii: in STD_LOGIC
...
In: in STD_LOGIC
I(n+1): in STD_LOGIC
I(n+2): in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L0 - 1} DOWNTO 0
Signal
is an output port.
Value
shows the Bit Level Sum of Products block parameters.
shows the Bit Level Sum of Products block I/O formats.
Direction
Input
Input
Output
The number of coefficients.
Specify the bit width as a signed integer. The bit width must be capable of
being expressed as a double in MATLAB.
Specify the coefficient values for each port as a sequence of signed integers.
the coefficient values must be capable of being expressed as a double in
MATLAB. For example: [-21 2 13 5]
When on, a register is added on the input signal.
Turn on to use the clock enable input (ena).
Turn on to use the synchronous clear input (sclr).
Preliminary
1 to 8 ports corresponding to the signed integer fixed coefficient
values specified in the block parameters.
Optional clock enable.
Optional synchronous clear.
Result.
(Note 1)
VHDL
Description
Description
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Bit Level Sum of Products
Explicit
Explicit
Type
(4)